Udemy - RTL Finite State Machines in System Verilog torrent

RTL Finite State Machines in System Verilog

https://DevCourseWeb.com

Published 10/2024
Created by Ninja S
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English | Duration: 35 Lectures ( 56m ) | Size: 382 MB

Finite State Machines are a fundamental building block in digital hardware designs.

What you'll learn:
Learn the design pattern for Register Transfer Level (RTL) descriptions of Finite State Machines in Digital Hardware
Hands on simulation of RTL Finite State Machine with a self checking test bench
Synthesis of RTL Finite State Machines
Optimization of RTL Finite State Machine to reduce Latency

Requirements:
Background in Digital Hardware Design (Electrical or Computer Engineering)
Exposure to an HDL (Verilog or VHDL) would be helpful
Taken course RTL Fundamentals in System Verilog (Recommended)